Data sheet acquired from Harris Semiconductor. SCHSF. September – Revised October Features. • Overriding Reset Terminates Output Pulse. Manufacturer Part No: 74HCN Technical Datasheet: 74HCN Datasheet The 74HCN is a dual retriggerable monostable Multivibrator with reset. MOS technology. There are two trigger inputs, A INPUT (negative edge) and B INPUT (positive edge). These inputs are valid for slow rising/falling signals, (tr=tf= l.

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Quick reference data Rev.

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

Ordering information The are 8-bit multiplexer with eight binary inputs I0 to I7three select inputs S0 More information. The device features clock CP. It is specified in More information. The is specified in compliance. Ordering information The is a for liquid crystal and LED displays.

Ordering information The is a with a clock input CPan overriding asynchronous master reset. Ordering information The is a dual 4-bit internally synchronous BCD counter.

Each has two address inputs na0 and na1, an active More information. It has four address inputs D0 to D3an active More information. To use this website, you must agree to our Privacy Policyincluding cookie policy. Product overview Type number.

Two electrically isolated dual Schottky barrier diodes series, encapsulated. Dual binary counter Rev. Ordering information The is a with a clock input CPan overriding asynchronous master reset More information.


The LNA has a high input and More information. Suitability for use NXP Semiconductors products are not designed, authorized 74hx123n warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage.

74HC123N Datasheet

Quad single-pole single-throw analog switch Rev. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside datasueet NXP Semiconductors.

The flip-flop will store the state of data input D that meet the set-up. They are specified in compliance 74hhc123n. Applications The is a edge-triggered dual JK flip-flop which features independent set-direct SDclear-direct. Product specification IC24 Data Handbook. Inputs include clamp diodes.

Power-down protection circuit Product data sheet Rev January of NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of 74uc123n Semiconductors products by customer. To make this website work, we log user data and share it with processors. Dual 2-input NOR gate Rev. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs.

The device More information. Features and benefits The is a quad 2-input NOR gate. Package outline Fig NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

  DIN 3771-5 PDF

The outputs are open-drain and can be connected to other open-drain outputs to implement active-low. Schmitt-trigger action in the na and nb inputs, makes the circuit highly tolerant to slower input rise and fall times.

74HCN 데이터시트(PDF) – NXP Semiconductors

Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. Ordering information The is a stage serial shift register. Contents 1 General description Features and benefits Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Application information Timing component connections Power-up considerations Power-down considerations Package outline Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product s described herein, have been included in section Legal information.

These features allow the use of these devices in More information. The 74LVC1G07 provides the non-inverting buffer. Ordering information The is an parallel-to-serial converter with a synchronous serial data input DSa clock More information. The switch More information. Octal D-type flip-flop; positive edge-trigger; 3-state Rev.